Since the invention of integrated circuits, the semiconductor industry has experienced continuous rapid growth due to constant improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in the minimum feature size, allowing more components to be integrated into a given chip area. These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limitations to the density that can be achieved in two dimensions. One of these limitations is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
To solve the above-discussed problems, three-dimensional integrated circuits (3DICs) and stacked dies are commonly used. The dies are stacked and the integrated circuits in the stacked dies are interconnected or routed through through-silicon vias (TSVs).
A known problem in the stacked dies is the heat dissipation. For example, when a top die is stacked to a bottom die, a heat sink may be mounted on the top die. Accordingly, the top die may have a good heat-dissipating ability. However, the heat generated in the bottom die needs to travel through the top die before it may reach the heat sink, and hence the bottom die may suffer from the heat-dissipating problem. The problem may become severe when the bottom die generates a lot of heat, for example, when the bottom die is a computing die, such as a central processing unit (CPU).